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  may 2007 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 FSQ100 ? green mode fairchild power switch (fps tm ) FSQ100 green mode fairchild power switch (fps tm ) features ? internal avalanche-rugged sensefet ? precision fixed oper ating frequency (67khz) ? burst-mode operation ? internal start-up circuit ? pulse-by-pulse current limiting ? over-voltage protection (ovp) ? overload protection (olp) ? internal thermal shutdown function (tsd) ? auto-restart mode ? under-voltage lockout (uvlo) with hysteresis ? built-in soft start ? secondary-side regulation applications ? charger & adapter for mobile phone, pda, mp3 ? auxiliary power for white goods, pc, c-tv, monitor related application notes ? an-4137 design guidelines for off-line flyback converters using fps? ? an-4141 troubleshooting and design tips for fairchild power switch (fps?) flyback applications ? an-4147 design guidelines for rcd snubber of flyback ? an-4134 design guidelines for off-line forward converters using fps? ? an-4138 design considerations for battery charger using green mode fairchild power switch (fps?) description the FSQ100 consists of an integrated pulse width modulator (pwm) and sensefet, specifically designed for high-performance, off-line, switch-mode power supplies (smps) with minimal external components. this device is an int egrated high-voltage power switching regulator that co mbines a vdmos sensefet with a voltage mode pwm cont rol block. the integrated pwm controller features in clude a fixed oscillator, under-voltage lockout (u vlo) protection, leading edge blanking (leb), an optimized gate turn-on/turn-off driver, thermal shutdown (tsd) protection, and temperature-compensated prec ision-current sources for loop compensation and fault protection circuitry. when compared to a discrete mosfet and controller or rcc solution, the FSQ100 device reduces total component count and design size and weight, while increasing efficiency, productivity, and system reliability. this device provides a basic platform well suited for cost-effective flyback converters. ordering information product number package marking code bv dss f osc r ds(on) FSQ100 8-dip q100 650v 67khz 16 ? fps tm is a trademark of fairchild semiconductor corporation.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 2 FSQ100 ? green mode fairchild power switch (fps tm ) typical application drain gnd vstr vfb v cc pwm ac in dc out figure 1. typical flyback application output power table open frame (1) product 230vac 15% (2) 85~265vac FSQ100 13w 8w notes: 1. maximum practical continuous power in an open- frame design with sufficient drain pattern as a heat sinker, at 50 c ambient. 2. 230vac or 100/115vac with doubler. internal block diagram 2 uvlo voltage ref v cc internal bias r sense i lim s/s 15ms 3 6,7,8 1 osc s r q tsd s r q leb olp a/r driver i delay 5 a i fb 400 a vck v th sfet drain gnd vfb burst v sd pwm min.20v ovp 4 nc 5 h vstr l 9/7v reset v burl / v burh figure 2. functional block diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 3 FSQ100 ? green mode fairchild power switch (fps tm ) pin assignments 1 2 3 45 6 7 8 gnd vcc vfb nc vstr drain drain drain figure 3. pin configuration (top view) pin definitions pin # name description 1 gnd ground . sensefet source terminal on prim ary side and internal control ground. 2 vcc positive supply voltage input . although connected to an auxiliary transformer winding, current is supplied from pin 5 (vstr) via an internal switch during start-up (see figure 2). when v cc reaches the uvlo upper threshold (9v), t he internal start-up switch opens and device power is supplied via the auxiliary transformer winding. 3 vfb feedback . inverting input to the pwm comparator wi th its normal input level lies between 0.5v and 2.5v. it has a 0.4ma current source connec ted internally, while a capacitor and opto- coupler are typically connected externally. a feedback voltage of 4. 5v triggers overload protection (olp). there is a time delay while charging external capacitor c fb from 3v to 4.5v using an internal 5a current source. this time delay prevents false tr iggering under transient conditions, but still allows the protection mec hanism to operate in true overload conditions. 4 nc no connection . 5 vstr start-up . this pin connects directly to the rectif ied ac line voltage sour ce. at start-up, the internal switch supplies internal bias and charges an external st orage capacitor placed between the vcc pin and ground. once the v cc reaches 9v, the internal switch stops charging the capacitor. 6,7,8 drain sensefet drain . the drain pins are designed to connect directly to the primary lead of the transformer and are capable of switching a maxi mum of 650v. minimizing the length of the trace connecting these pins to the tr ansformer decreases leakage inductance.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 4 FSQ100 ? green mode fairchild power switch (fps tm ) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. t a = 25c, unless otherwise specified. symbol parameter value unit v drain drain pin voltage 650 v v str vstr pin voltage 650 v v dg drain-gate voltage 650 v v gs gate-source voltage 20 v v cc supply voltage 20 v v fb feedback voltage range -0.3 to v stop v p d total power dissipation 1.40 w t j operating juncti on temperature internally limited c t a operating ambient temperature -25 to +85 c t stg storage temperature -55 to +150 c notes: 1. repetitive rating: pulse width is limited by maximum junction temperature. 2. l = 24mh, starting t j = 25 c. thermal impedance t a = 25c, unless otherwise specified. all items are tested with the jede c standards jesd 51-2 and 51-10 (dip). symbol parameter value unit ja junction-to-ambient thermal impedance (3) 88.84 c/w jc junction-to-case thermal impedance (4) 13.94 c/w notes: 3. free-standing with no heatsink; without copper clad. measurement condition ? just before junction temperature t j enters into otp. 4. measured on the drain pin cl ose to plastic interface.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 5 FSQ100 ? green mode fairchild power switch (fps tm ) electrical characteristics t a = 25c, unless otherwise specified. symbol parameter conditions min. typ. max. unit sensefet section v ds =650v, v gs =0v 25 i dss zero-gate-voltage drain current v ds =520v, v gs =0v, t c =125 c 200 a r ds(on) drain-source on-state resistance (5) v gs =10v, i d =0.5a 16 22 ? g fs forward trans-conductance v ds =50v, i d =0.5a 1.0 1.3 s c iss input capacitance 162 c oss output capacitance 18 c rss reverse transfer capacitance v gs =0v, v ds =25v, f=1mhz 3.8 pf control section f osc switching frequency 61 67 73 khz f osc switching frequency variation (6) -25c t a 85c 5 10 % d max maximum duty cycle 60 67 74 % v start v fb =gnd 8 9 10 v v stop uvlo threshold voltage v fb =gnd 6 7 8 v i fb feedback source current 0v v fb 3v 0.35 0.40 0.45 ma t s/s internal soft start time 10 15 20 ms burst mode section v burh 0.6 0.7 0.8 v v burl t j =25c 0.45 0.55 0.65 v v bur(hys) burst mode voltage hysteresis 150 mv protection section i lim peak current limit 0.475 0.550 0.650 a t sd thermal shutdown temperature (7) 125 145 c v sd shutdown feedback volt age 4.0 4.5 5.0 v v ovp over-voltage protection 20 v i delay shutdown delay current 3v v fb v sd 4 5 6 a total device section i op operating supply current (8) v cc 16v 1.5 3.0 ma i ch start-up charging current v cc =0v , v str =50v 450 550 650 a notes: 5. pulse test: pulse width 300s, duty 2%. 6. these parameters, alt hough guaranteed, are tested in ed s (wafer test) process. 7. these parameters, al though guaranteed, are not 100% tested in production. 8. control part only.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 6 FSQ100 ? green mode fairchild power switch (fps tm ) typical performance characteristics these characteristic graphs are normalized at t a = 25c. -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] v ovp -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] i op figure 4. over-voltage protection (v ovp ) vs. t a figure 5. operating supply current (i op ) vs. t a -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] v staart -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] v stop figure 6. start threshold voltage (v start ) vs. t a figure 7. stop threshold voltage (v stop ) vs. t a -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] f osc -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] d max figure 8. operating frequency (f osc ) vs. t a figure 9. maximum duty cycle (d max ) vs. t a
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 7 FSQ100 ? green mode fairchild power switch (fps tm ) typical performance characteristics (continued) these characteristic graphs are normalized at t a = 25c. -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] i lim -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] i fb figure 10. peak current limit (i lim ) vs. t a figure 11. feedback source current (i fb ) vs. t a -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] i delay -50 0 50 100 150 0.85 0.90 0.95 1.00 1.05 1.10 1.15 temperature [c] v sd figure 12. shutdown delay current (i delay ) vs. t a figure 13. shutdown feedback voltage (v sd ) vs. t a
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 8 FSQ100 ? green mode fairchild power switch (fps tm ) functional description 1. start-up: at start-up, the inter nal high-voltage current source supplies the inter nal bias and charges the external v cc capacitor, as shown in figure 14. when v cc reaches 9v, the device starts switching and the internal high-voltage current source stops charging the capacitor. the device is in normal operation provided v cc does not drop below 7v. afte r start-up, the bias is supplied from the auxiliary transformer winding. v in ,dc vstr v cc i str 9v/ 7v l h figure 14. internal start-up circuit calculating the v cc capacitor is an important step to design with the FSQ100. at in itial start-up, the maximum value of start operating current i start is about 100a, which supplies current to uvlo and v ref blocks. the charging current i vcc of the v cc capacitor is equal to i str ? 100a. after v cc reaches the uvlo start voltage, only the bias winding supplies v cc current to the device. when the bias winding voltage is not sufficient, the v cc level decreases to the uvlo stop voltage and the internal current source is activated again to charge the v cc capacitor. to prevent this v cc fluctuation (charging/discharging), the v cc capacitor should be chosen to have a value between 10f and 47f. v in ,dc vstr i str j-fet uvlo v ref i start i vcc =i str -i start i vcc =i str -i start v cc v start v stop t v cc v cc must not drop below v stop bias winding voltage uvlo figure 15. charging v cc capacitor through vstr 2. feedback control: the FSQ100 is a voltage mode controlled device, as show n in figure 16. usually, an opto-coupler and shunt regul ator, like ka431 are used to implement the feedba ck network. the feedback voltage is compared with an internally generated sawtooth waveform. this direct ly controls the duty cycle. when the shunt regulator re ference pin voltage exceeds the internal reference volt age of 2.5v, the opto-coupler led current increases , the feedback voltage v fb is pulled down, and it reduces the duty cycle. this happens when the input voltage increases or the output load decreases. 4 osc v cc v ref 5a v sd r gate driver olp v fb ka431 c fb v o + v fb 400a figure 16. pwm and feedback circuit 3. leading edge blanking (leb): at the instant the internal sensefet is tu rned on, the primary-side capacitance and secondary-side rectifier diode reverse recovery typically causes a high-current spike through the sensefet. excessive voltage across the r sense resistor lead to incorrect pulse-by-pulse current limit protection. to avoid this, a leading edge blanking (leb) circuit disables pulse-by-pul se current-limit protection block for a fixed time (t leb ) after the sensefet turns on. 4. protection circuit: the FSQ100 has protective functions, such as overl oad protection (olp), over voltage protection (ovp), unde r-voltage lockout (uvlo), and thermal shutdown (tsd). because these protection circuits are fully integrated in side the ic without external components, reliability is im proved without increasing costs. once a fault condition occurs, switching is terminated and the sensefet remains off. this causes v cc to fall. when v cc reaches the uvlo stop voltage v stop (7v), the protection is reset and the internal high- voltage current sour ce charges the v cc capacitor via the vstr pin. when v cc reaches the uvlo start voltage v start (9v), the device resumes normal operation. in this manner, the auto-restar t can alternately enable and disable the switching of t he power sensefet until the fault condition is eliminated. osc 4 v fb s r q gate driver olp, tsd protection block 5 a 4 0 0 a reset 4.5 v olp + - tsd s r q a/r c fb r figure 17. protection block
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 9 FSQ100 ? green mode fairchild power switch (fps tm ) 4.1 overload protection (olp): overload is defined as the load current exceeding a pre-set level due to an unexpected event. in this situat ion, the protection circuit should be activated to prot ect the smps. however, even when the smps is operat ing normally, the over load protection (olp) circuit can be activated during the load transition. to avoid this undesired operation, the olp circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. if the output consumes more than the maximum power determined by i lim , the output voltage (v o ) decreases below its rating voltage. this reduces the current thr ough the opto-coupler led, which also reduces the opto- coupler transistor current, thus increasing the feedback voltage (v fb ). if v fb exceeds 3v, the feedback input diode is blocked and the 5a current source (i delay ) starts to charge c fb slowly up to v cc . in this condition, v fb increases until it reaches 4.5v, when the switching oper ation is terminated, as shown in figure 18. the shutdown delay time is the time required to charge c fb from 3v to 4.5v with a 5a current source. v fb t 3v 4.5v overload protection t 12 =cfb(v( t 2 )-v( t 1 )) / i delay t 1 t 2 v t v v t v a i i t v t v c fb t delay delay 5 . 4 ) ( , 3 ) ( , 5 ; ) ( ) ( 2 1 1 2 12 = = = ? = figure 18. overload protection (olp) 4.2 thermal shutdown (tsd): the sensefet and the control ic are integrated, ma king it easier for the control ic to detect the temperat ure of the sensefet. when the temperature exc eeds approximately 145 c, thermal shutdown is activated. 5. soft-start: the fps has an internal soft-start circuit that slowly increases the feedback voltage, together with the sensefet current, right after it starts. the typical soft-start time is 15ms, as shown in figure 19, where progressive increment of the sensefet current is allowed during the start-up phase. soft-start circuit progressively increases current limits to establish proper working conditions for transformers, inductors, capacitors, and switching devices. it also helps to prevent transformer saturation and reduces the stress on the secondary diode. 2.14ms 7steps 0.31a 0.55a t drain current figure 19. internal soft-start 6. burst operation: to minimize the power dissipation in standby mode, the FSQ100 enters burst-mode operation. as the load dec reases, the feedback voltage decreases. the device automat ically enters burst mode when the feedback voltage drops below v burl (0.55v). at this point, switching stops and the out put voltages start to drop. this causes the feedback voltage to rise. once is passes v burh (0.70v), switching starts again. the feedback voltage falls and the process repeats. burst-mode operation alter nately enables and disables switching of the power mosf et to reduce the switching loss in standby mode. osc 4 v fb s r q gate driver 5a 400a 0.7 0 v /0.55v on /off burst operation block figure 20. burst operation block v fb v ds 0.55v 0. 70v i ds v o v o set t figure 21. burst operation function
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 10 FSQ100 ? green mode fairchild power switch (fps tm ) application tips 1. methods of reducing audible noise switching mode power converters have electronic and magnetic components that generate audible noise when the operating frequency is in the range of 20~20,000hz. even though they operate above 20khz, they can make noise, depending on the load condition. designers can employ several methods to reduce noise. glue or varnish the most common method involves using glue or varnish to tighten magnetic components. the motion of core, bobbin and coil, and the chattering or magnetostriction of core c an cause the transformer to produce audible noise. the use of rigid glue and varnish helps reduce the transformer noise, but can crack the core. this is because s udden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio. ceramic capacitor using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise-reduction solution. some dielectric materials show a piezoelectric effect, depending on the electric fiel d intensity. hence, a snubber capacitor becomes one of the most significant sources of audible noise. it is possible to use a zener clamp circuit instead of an rcd snubber for higher efficiency as and lower audible noise. adjusting sound frequency moving the fundamental fr equency of noise out of 2~4khz range is the third method. generally, humans are more sensitive to noise in the range of 2~4khz. when the fundamental frequency of noise is located in this range, the noise is perceived as louder, although the noise intensity level is identical (refer to figure 22 equal loudness curves). when fps acts in burst m ode and the burst operation is suspected to be a source of noise, this method may be helpful. if the frequency of burst-mode operation lies in the range of 2~4 khz, adj usting the feedback loop can shift the burst operation fr equency. to reduce the burst operation frequency, increase a feedback gain capacitor (c f ), opto-coupler supply resistor (r d ), and feedback capacitor (c b ); and decrease a feedback gain resistor (r f ), as shown in figure 23. figure 22. equal loudness curves figure 23. typical feedback network of fps? 2. reference materials an-4134 : design guidelines for off-line forward converters using fairchild power switch (fps tm ) an-4137 : design guidelines for off-line flyback converters using fairchild power switch (fps tm ) an-4138 : design considerations for battery charger using green mode fairchild power switch (fps tm ) an-4140 : transformer design consideration for off-line flyback converters using fairchild power switch (fps tm ) an-4141 : troubleshooting and design tips for fairchild power switch (fps tm ) flyback applications an-4147 : design guidelines for rcd snubber of flyback an-4148 : audible noise reduction techniques for fps tm applications
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 11 FSQ100 green mode fairchild power switch (fps tm ) physical dimensions dimensions are in millimeters and in ches unless otherwise noted. figure 24. 8-pin dual inline package (dip)
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FSQ100 rev. 1.0.1 12 FSQ100 green mode fairchild power switch (fps tm )


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